? semiconductor components industries, llc, 2009 april, 2009 ? rev. 0 1 publication order number: ADP3121/d ADP3121 dual bootstrapped, 12 v mosfet driver with output disable the ADP3121 is a dual, high voltage mosfet driver optimized for driving two n ? channel mosfets, the two switches in a non ? isolated synchronous buck power converter. each driver is capable of driving a 3000 pf load with a 20 ns propagation delay and a 15 ns transition time. one of the drivers can be bootstrapped and is designed to handle the high voltage slew rate associated with floating high ? side gate drivers. the ADP3121 includes overlapping drive protection to prevent shoot ? through current in the external mosfets. the od pin shuts off both the high ? side and the low ? side mosfets to prevent rapid output capacitor discharge during system shutdown. the ADP3121 is specified over the commercial temperature range of 0 c to 85 c and is available in 8 ? lead soic_n and 8 ? lead lfcsp packages. features ? all ? in ? one synchronous buck driver ? bootstrapped high ? side drive ? one pwm signal generates both drives ? anticross conduction protection circuitry ? over voltage protection ? od for disabling the driver outputs ? meets cpu vr requirement when used with flex ? mode ? controller ? these are pb ? free devices typical applications ? multiphase desktop cpu supplies ? single ? supply synchronous buck converters device package shipping ? ordering information soic_n (pb ? free) 2500/tape & reel ADP3121jrz ? rl lfcsp_vd (pb ? free) 5000/tape & reel ADP3121jcpz ? rl http://onsemi.com 1 8 p3121 alyw 1 8 p3121 = specific device code al = assembly location y = year w = work week = pb ? free package lfcsp8 mn suffix case 932af so ? 8 d suffix case 751 1 l7q #yww l7q = specific device code y = year ww = work week = pb ? free package 8 ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d.
ADP3121 http://onsemi.com 2 pin connections drvh swn pgnd drvl bst in od v cc figure 1. block diagram in ADP3121 bst drvh sw drvl pgnd delay 6 delay cmp cmp 1v 4 1 7 control logic 6 5 8 12v q1 to inductor q2 latch q s d1 2 3 od r bst r g c bst1 c bst2 r1 r2 v cc v cc pin function description pin no. pin name description 1 bst upper mosfet floating bootstrap supply. a capacitor connected between the bst and sw pins holds this bootstrapped voltage for the high ? side mosfet while it is switching. 2 in logic level pwm input. this pin has primary control of the drive outputs. in normal operation, pulling this pin low turns on the low ? side driver; pulling it high turns on the high ? side driver. 3 od output disable. when low, this pin disables normal operation, forcing drvh and drvl low. 4 vcc input supply. this pin should be bypassed to pgnd with an ~1 f ceramic capacitor. 5 drvl synchronous rectifier drive. output drive for the lower (synchronous rectifier) mosfet. 6 pgnd power ground. this pin should be closely connected to the source of the lower mosfet. 7 sw switch node connection. this pin is connected to the buck switching node, close to the upper mosfet source. it is the floating return for the upper mosfet drive signal. it is also used to monitor the switched voltage to prevent the lower mosfet from turning on until the voltage is below ~1 v. 8 drvh buck drive. output drive for the upper (buck) mosfet.
ADP3121 http://onsemi.com 3 maximum ratings rating value unit ja , soic_n 2 ? layer board 123 c/w 4 ? layer board 90 c/w ja , lfcsp_vd (note 1) 4 ? layer board 64.3 c/w operating ambient temperature range 0 to 85 c junction temperature range 0 to 150 c storage temperature range ? 65 to +150 c lead temperature soldering (10 sec) 300 c vapor phase (60 sec) 215 c infrared (15 sec) 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. internally limited by thermal shutdown, 150 c min. 2. 2 layer board, 1 in 2 cu, 1 oz thickness. 3. 60 ? 180 seconds minimum above 237 c. 4. this device is esd sensitive. use standard esd precautions when handling absolute maximum ratings pin symbol pin name v max v min v cc main supply voltage input 15 v ? 0.3 v gnd ground 0 v 0 v bst bootstrap supply voltage input dc v cc + 15 ? 0.3 v <200 ns +35 ? 0.3 v bst to sw +15 ? 0.3 v sw switching node (bootstrap supply return) dc +15 ? 5 v <200 ns +25 v ? 10 v drvh high ? side driver output dc <20 ns bst + 0.3 bst + 2 v sw ? 0.3 v sw ? 2 v <200 ns bst + 0.3 v sw ? 2 v drvl low ? side driver output dc <20 ns v cc + 0.3 v v cc + 2 v ? 0.3 v ? 2 v <200 ns v cc + 0.3 v ? 2 v in drvh and drvl control input 6.5 v ? 0.3 v od outside disable 6.5 v ? 0.3 v note: all voltages are with respect to pgnd except where noted. stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability.
ADP3121 http://onsemi.com 4 electrical characteristics (v cc = 12 v, bst = 4 v to 26 v, t a = 0 c to 85 c, unless otherwise noted) (note 5) characteristic test conditions symbol min typ max unit supply supply voltage range v cc 4.15 13.2 v supply current bst = 12 v, in = 0 v i sys 2 5 ma od inputs input voltage high 2.0 v input voltage low 0.8 v input current ? 1 +1 a hysteresis 90 250 mv pwm inputs input voltage high 2.0 v input voltage low 0.8 v input current ? 1 +1 a hysteresis 90 250 mv high ? side driver output resistance, sourcing current bst ? sw = 12 v; t a = 25 c 2.3 bst ? sw = 12 v; t a = 0 c to 85 c 1.7 2.8 output resistance, sinking current bst ? sw = 12 v; t a = 25 c 2.3 bst ? sw = 12 v; t a = 0 c to 85 c 1.7 2.8 output resistance, unbiased bst ? sw = 0 v 10 k transition times bst ? sw = 12 v, c load = 3 nf, see figure 4 t rdrvh 20 32 ns bst ? sw = 12 v, c load = 3 nf, see figure 4 t fdrvh 20 30 ns propagation delay times bst ? sw = 12 v, c load = 3 nf t pdhdrvh 20 30 50 ns 25 c t a 85 c, see figure 4 bst ? sw = 12 v, c load = 3 nf, see figure 4 t pdldrvh 32 47 ns see figure 3 t pdlod 30 45 ns see figure 3 t pdhod 20 40 ns sw pull ? down resistance sw to pgnd 10 k low ? side driver output resistance, sourcing current t a = 25 c 2.4 t a = 0 c to 85 c 1.8 2.8 output resistance, sinking current t a = 25 c 1.6 t a = 0 c to 85 c 1.0 1.8 output resistance, unbiased v cc = pgnd 10 k transition times c load = 3 nf, see figure 4 t rdrvl 20 30 ns c load = 3 nf, see figure 4 t fdrvl 10 20 ns propagation delay times c load = 3 nf, see figure 4 t pdhdrvl 15 35 ns c load = 3 nf, see figure 4 t pdldrvl 17 32 ns see figure 3 t pdlod 37 52 ns see figure 3 t pdhod 100 180 ns 5. all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc) methods
ADP3121 http://onsemi.com 5 electrical characteristics (v cc = 12 v, bst = 4 v to 26 v, t a = 0 c to 85 c, unless otherwise noted) (note 5) characteristic unit max typ min symbol test conditions low ? side driver timeout delay sw = 5 v sw = pgnd 90 70 170 110 ns over ? voltage protection threshold in = od = 0 v, s w = v cc v sw(ovd) 1.5 3.5 v undervoltage lockout uvlo voltage v cc rising 1.5 3.0 v hysteresis 250 mv 5. all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc) methods applications information theory of operation the ADP3121 is optimized for driving two n ? channel mosfets in a synchronous buck converter topology. a single pwm input signal is all that is required to properly drive the high side and the low ? side mosfets. each driver is capable of driving a 3 nf load at speeds up to 500 khz. a functional block diagram of ADP3121 is shown in figure 1. low ? side driver the low ? side driver is designed to drive a ground referenced n ? channel mosfet. the bias to the low ? side driver is internally connected to the v cc supply and pgnd. when the driver is enabled, the driver output is 180 out of phase with the pwm input. when the ADP3121 is disabled, the low ? side gate is held low. high ? side driver the high ? side driver is designed to drive a floating n ? channel mosfet. the bias voltage for the high ? side driver is developed by an external bootstrap supply circuit that is connected between the bst and sw pins. the bootstrap circuit comprises diode d1 and bootstrap capacitor c bst1 . c bst2 and r bst are included to reduce the high ? side gate drive voltage and to limit the switch node slew rate (called a boot ? snap circuit). when the ADP3121 starts up, the sw pin is at ground, so the bootstrap capacitor charges up to v cc through d1. when the pwm input goes high, the high ? side driver begins to turn on the high ? side mosfet, q1, by pulling charge out of c bst1 and c bst2 . as q1 turns on, the sw pin rises up to v in and forces the bst pin to v in + v c (bst) . this holds q1 on because enough gate ? to ? source voltage is provided. to complete the cycle, q1 is switched off by pulling the gate down to the voltage at the sw pin. when the low ? side mosfet, q2, turns on, the sw pin is pulled to ground. this allows the bootstrap capacitor to charge up to v cc again. the output of the high ? side driver is in phase with the pwm input. when the driver is disabled, the high ? side gate is held low. overlap protection circuit the overlap protection circuit prevents both of the main power switches, q1 and q2, from being on at the same time. this is done to prevent shoot ? through currents from flowing through both power switches and the associated losses that can occur during their on/off transitions. the overlap protection circuit accomplishes this by adaptively controlling the delay from the q1 turn ? off to the q2 turn ? on, and by internally setting the delay from the q2 turn ? off to the q1 turn ? on. to prevent the overlap of the gate drives during the q1 turn ? off and the q2 turn ? on, the overlap circuit monitors the voltage at the sw pin. when the pwm input signal goes low, q1 begins to turn off (after propagation delay). before q2 can turn on, the overlap protection circuit makes sure that sw has first gone high and then waits for the voltage at the sw pin to fall from v in to 1 v. once the voltage on the sw pin falls to 1 v, q2 begins turn ? on. if the sw pin has not gone high first, the q2 turn ? on is delayed by a fixed 150 ns. by waiting for the voltage on the sw pin to reach 1 v or for the fixed delay time, the overlap protection circuit ensures that q1 is of f before q2 turns on, regardless of variations in temperature, supply voltage, input pulse width, gate charge, and drive current. if sw does not go below 1 v after 190 ns, drvl turns on. this can occur if the current flowing in the output inductor is negative and flows through the high ? side mosfet body diode. overvoltage protection the ADP3121 includes an over ? voltage protection (ovp) feature to protect the cpu from high voltages even before the main controller has enough vcc to operate. the ADP3121 looks at the sw node during startup. if the voltage on sw is greater than the ovp threshold, drvl is latched on and drvh latched off. an ovp on the sw node will cause drvl to go high and remain high. to prevent false triggering of ovp, an input logic detection latch is set on the first occurrence of either in or
ADP3121 http://onsemi.com 6 od going high. if this second latch is set, then ovp is enabled. to clear the ovp or the input detected latch, v cc must fall below uvlo. supply capacitor selection for the supply input (v cc ) of the ADP3121, a local bypass capacitor is recommended to reduce the noise and to supply some of the peak currents that are drawn. use a 4.7 f, low esr capacitor. multilayer ceramic chip (mlcc) capacitors provide the best combination of low esr and small size. keep the ceramic capacitor as close as possible to the ADP3121. bootstrap circuit the bootstrap circuit uses a charge storage capacitor (c bst ) and a diode, as shown in figure 1. these components can be selected after the high ? side mosfet is chosen. the bootstrap capacitor must have a voltage rating that can handle twice the maximum supply voltage. a minimum 50 v rating is recommended. the capacitor values are determined by c bst1 c bst2 10 q gate v gate (eq. 1) c bst1 c bst1 c bst2 v gate v cc v d (eq. 2) where: q gate is the total gate charge of the high ? side mosfet at v gate . v gate is the desired gate drive voltage (usually in the range of 5 v to 10 v, 7 v being typical). v d is the voltage drop across d1. rearranging equation 1 and equation 2 to solve for c bst1 yields c bst1 10 q gate v cc v d c bst2 can then be found by rearranging equation 1 c bst2 10 q gate v gate c bst1 for example, an ntd60n02 has a total gate charge of about 12 nc at v gate = 7 v. using v cc = 12 v and v d = 0.1 v, then c bst1 = 12 nf and c bst2 = 6.8 nf. good quality ceramic capacitors should be used. r bst is used to limit slew rate and minimize ringing at the switch node. it also provides peak current limiting through d1. an r bst value of 1.5 to 2.2 is a good choice. the resistor needs to handle at least 250 mw due to the peak currents that flow through it. a small signal diode can be used for the bootstrap diode due to the ample gate drive voltage supplied by v cc . the bootstrap diode must have a minimum 15 v rating to withstand the maximum supply voltage. the average forward current can be estimated by i f(avg) q gate f max (eq. 3) where f max is the maximum switching frequency of the controller. the peak surge current rating should be calculated by i f(peak) v cc v d r bst (eq. 4) mosfet selection when interfacing the ADP3121 to external mosfets, the designer should consider ways to make a robust design that minimizes stresses on both the driver and the mosfets. these stresses include exceeding the short time duration voltage ratings on the driver pins as well as the external mosfet. it is also highly recommended to use the boot ? snap circuit to improve the interaction of the driver with the characteristics of the mosfets. if a simple bootstrap arrangement is used, make sure to include a proper snubber network on the sw node. high ? side (control) mosfets a high ? side, high speed mosfet is usually selected to minimize switching losses (see the adp3186 or adp3188 data sheet for flex ? mode controller details). this typically implies a low gate resistance and low input capacitance/charge device. yet, a significant source lead inductance can also exist that depends mainly on the mosfet package; it is best to contact the mosfet vendor for this information. the ADP3121 drvh output impedance and the input resistance of the mosfets determine the rate of charge delivery to the internal capacitance of the gate. this determines the speed at which the mosfets turn on and off. however, because of potentially large currents flowing in the mosfets at the on and off times (this current is usually larger at turn ? off due to ramping up of the output current in the output inductor), the source lead inductance generates a significant voltage when the high ? side mosfets switch off. this creates a significant drain ? source voltage spike across the internal die of the mosfets and can lead to a catastrophic avalanche. the mechanisms involved in this avalanche condition are referenced in literature from the mosfet suppliers. the mosfet vendor should provide a rating for the maximum voltage slew rate at drain current around which this can be designed. once this specification is obtained, determine the maximum current expected in the mosfet by i max i dc (per phase) (v cc v out ) d max f max l out (eq. 5) where: d max is determined for the vr controller being used with the driver. this current is divided roughly equally between mosfets if more than one is used (assume a worst ? case mismatch of 30% for design margin). l out is the output inductor value.
ADP3121 http://onsemi.com 7 when producing the design, there is no exact method for calculating the dv/dt due to the parasitic effects in the external mosfets as well as the pcb. however, it can be measured to determine if it is safe. if it appears that the dv/dt is too fast, an optional gate resistor can be added between drvh and the high ? side mosfets. this resistor slows down the dv/dt, but it increases the switching losses in the high ? side mosfets. the ADP3121 is optimally designed with an internal drive impedance that works with most mosfets to switch them ef ficiently, yet minimizes dv/dt. however, some high speed mosfets can require this external gate resistor depending on the currents being switched in the mosfet. low ? side (synchronous) mosfets the low ? side mosfets are usually selected to have a low on resistance to minimize conduction losses. this usually implies a large input gate capacitance and gate charge. the first concern is to make sure the power delivery from the ADP3121 drvl does not exceed the thermal rating of the driver (see the adp3186, adp3188, or adp3189 data sheets for flex ? mode controller details). the next concern for the low ? side mosfets is to prevent them from being inadvertently switched on when the high ? side mosfet turns on. this occurs due to the drain ? gate (miller capacitance, also specified as c rss capacitance) of the mosfet. when the drain of the low ? side mosfet is switched to v cc by the high ? side turning on (at a dv/dt rate), the internal gate of the low ? side mosfet is pulled up by an amount roughly equal to v cc (c rss /c iss ). it is important to make sure this does not put the mosfet into conduction. another consideration is the nonoverlap circuitry of the ADP3121 that attempts to minimize the nonoverlap period. during the state of the high ? side turning off to low ? side turning on, the sw pin is monitored (as well as the conditions of sw prior to switching) to adequately prevent overlap. however, during the low ? side turn ? off to high ? side turn ? on, the sw pin does not contain information for determining the proper switching time, so the state of the drvl pin is monitored to go below one sixth of v cc ; then, a delay is added. due to the miller capacitance and internal delays of the low ? side mosfet gate, ensure that the miller ? to ? input capacitance ratio is low enough, and that the low ? side mosfet internal delays are not so large as to allow accidental turn ? on of the low ? side when the high ? side turns on. contact on semiconductor for an updated list of recommended low ? side mosfets. pc board layout considerations use these general guidelines when designing printed circuit boards: ? trace out the high current paths and use short, wide (>20 mil) traces to make these connections. ? minimize trace inductance between drvh and drvl outputs and mosfet gates. ? connect the pgnd pin of the ADP3121 as closely as possible to the source of the lower mosfet. ? locate the v cc bypass capacitor as close as possible to the v cc and pgnd pins. ? use vias to other layers, when possible, to maximize thermal conduction away from the ic. figure 2 shows an example of the typical land patterns based on the guidelines given previously. for more detailed layout guidelines for a complete cpu voltage regulator subsystem, refer to the pc board layout considerations section of the adp3188 data sheet. figure 2. external component placement example c vcc c bst1 c bst2 r bst
ADP3121 http://onsemi.com 8 figure 3. output disable timing diagram figure 4. timing diagram od drvh or drvl 90% t pdlod 10% t pdhod sw drvh ? sw drvl in t pdldrvl t fdrvl t pdldrvh t rdrvl t fdrvh v th v th 1 v t pdhdrvl t pdhdrvh t rdrvh
ADP3121 http://onsemi.com 9 package dimensions soic ? 8 nb case 751 ? 07 issue aj seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
ADP3121 http://onsemi.com 10 package dimensions lfcsp8 3x3, 0.5p case 932af ? 01 issue o seating note 4 m 0.25 c (a3) a a1 d2 b 1 8 e2 8x 4x l 8x bottom view indicator top view side view d a b e 0.25 c pin one reference 0.10 c 0.08 c c e a 0.10 b c 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimensions: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. dim min max millimeters a 0.80 0.90 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 1.59 1.89 e 3.00 bsc 1.60 e2 1.30 e 0.50 bsc h ??? 12 k 0.20 ??? plane dimensions: millimeters 0.50 1.90 0.30 1.61 8x 0.63 8x 3.30 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 1 l 0.30 0.50 m ??? 0.60 d1 2.75 bsc e1 2.75 bsc d1 e1 h pitch package outline pin 1 m 4x k note 3 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ADP3121/d flex ? mode is protected by u.s. patent 6683441; other patents pending. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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